1. Field of the Invention
The present invention relates to an output buffer circuit capable of controlling the through rate of a wave form of an output voltage to be provided to external devices connected to an output terminal of the output buffer circuit.
2. Description of the Prior Art
FIG. 5 is a block diagram showing a configuration of a conventional output buffer circuit capable of controlling through rate of a wave form of an output voltage (hereinafter referred to as "an output wave form") to be provided to external devices (not shown) connected to an output terminal 66 of the output buffer circuit. In FIG. 5, the reference number 65 designates an input terminal. The reference numbers 57 to 60 denote output transistors for outputting a high voltage level (a H voltage level). The reference numbers 61 to 64 denote output transistors for outputting a low voltage level (a L voltage level). The reference numbers 51 to 56 indicate delay circuits, and 66 designates an output terminal.
Next, a description will be given of the operation of the conventional output buffer circuit and drawbacks thereof having the configuration described above.
In the basic operation of the conventional output buffer circuit shown in FIG. 5, the through rate of an output wave form of an output voltage provided through the output terminal 66 to external devices (omitted from FIG. 5) in the conventional output buffer circuit may be controlled by switching the H level output transistors 57 to 60 and the L level output transistors 61 to 64 into ON state based on a time difference among time values that have been set in advance in the delay circuits 51 to 56, respectively. However, this configuration has a drawback in which the through rate of the output wave form of an output voltage provided through the output terminal 66 is changed according to the magnitude of a total load capacity of the external devices connected to the output terminal 66 because each of the output transistors 58 to 60 and 62 to 64 operates based on the fixed delay time that has been set in advance in each of the delay circuits 51 to 56. Therefore the through rate of the wave form of the output voltage is changed according to the change of the magnitude of the total load capacity of the devices.
FIG. 4 is a diagram showing various wave forms of output voltages provided from the conventional output buffer circuit designated by the dotted lines E to H and from an improved output buffer circuit as the present invention designated by the solid lines. The feature of the output buffer circuit according to the present invention indicated by the solid lines A to D will be explained in the following section, namely, "DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT".
In FIG. 4, the dotted lines E to H indicate the output waves forms of the various output voltages provided from the conventional output buffer circuit. In FIG. 4, the horizontal axis indicates time (nano seconds) and the vertical axis denotes a voltage (Volts). The dotted lines in FIG. 4 show the changes of the through rate of the output wave form provided from the conventional output buffer circuit caused by the change of the magnitude of the load capacity of the external devices connected to the output terminal 66. As shown in FIG. 4, the output wave form E shows the case when the magnitude of the load capacity is g 5 pF, the output wave form F indicates the case of 10 pF, the output wave form G indicates the case of 15 pF, and the output wave form H indicates the case of 20 pF.
In the conventional output buffer circuit, because each of the transistors 58 to 60 and 62 to 64 turns ON based on the fixed delay time even if the change of a transistor characteristic of each of the output transistors 58 to 60 and 62 to 64 is caused by the fluctuation of ambient temperature, there is a drawback that the through rate of the output wave form of the output voltage is changed according to the change of the transistor characteristic caused by the fluctuation of ambient temperature.